To improve the functionality of integrated chips, the semiconductor industry has continually increased the number of transistors that are on an integrated chip. To achieve a larger number of transistors on an integrated chip, without substantially increasing a size of the integrated chip, the semiconductor industry has continually reduced the minimum feature size of integrated chip components. For example, the minimum gate width of a transistor has been reduced from tens of microns in the 1980s to tens of nanometers in advanced technology nodes (e.g., in 22 nm nodes, 16 nm nodes, etc.).
However, next generation lithographic exposure tools have failed to keep pace with the demand for shrinking, and integrated chips in advanced technology nodes have minimum feature sizes that are far less than the wavelength of radiation used in lithographic exposure tools. Therefore, to achieve small minimum feature sizes, lithographic exposure tools have been forced to use tricks to reduce the minimum feature sizes. Double-patterning lithography (DPL) has emerged as one of the most promising solutions to continue scaling in advanced processing nodes.